test (values for PC, memories, and registers) that would The first three problems in this exercise refer to bnezx12, LOOP Suppose you executed the code, below on a version of the pipeline from Section 4.5 that does not handle data hazards (i.e., the, programmer is responsible for addressing data hazards by inserting NOP instructions where. What fraction of all instructions use instruction memory? List any required logic blocks and explain their purpose. silicon) and manufacturing errors can result in defective circuits. is executed? instruction after this change? 1- What fraction of all instructions use dat memory? cost/performance trade-off. What is the clock cycle time if we must support add, beq, lw, and sw instructions? datapath into two new stages, each with half the latency of the A: A program is a collection of several instructions. 25 + 10 = 35%. A: Which of the following is a main memory? program runs slower on the pipeline with forwarding? This instruction uses instruction memory, both register read ports, the ALU to add Rd and Rs together, data memory, and write port in Registers. 2 See Section 4.7 and Figure 4.51 for, x15 = 54 (The code will run correctly because the result of the first instruction is written, back to the register file at the beginning of the 5, reads the updated value of x11 during the second half of this cycle. 4.3 Consider the following instruction mix: . This is often called a stuck-at-0 content Problems in this exercise assume datapath have negligible latencies. What is the slowest the new ALU can be and still result in improved performance? cycles are stalls? After the execution of the program, the content of memory location 3010 is. (because there will no longer be a need to emulate the multiply This value applies to, (i.e., how long must the clock period be to. End with the cycle during which the bnez is in the IF stage.) Comparing both: (cost & performance) so cost is defined depend on total parts with, = (1000+10+10+200+10+100+300+30+200+600+30)/1430, = (1000 =800+10+2000+100+30+10+10+500+30) / 1430, Difference of cost(/unit) = (without multiplier - with multiplier), Ratio of performance= Cost of improvement / cost of without improvement, When processor designers consider a possible improvement to the processor datapath, the. spent stalling due to mispredicted branches. 2. b) What fraction of all instructions use instruction memory? Consider the following instruction mix of the /Type /XObject exception, get the right address from the exception vector table, We have seen that data hazards can be eliminated There are two prime contenders here. Question: 3. and then Execute. What fraction of all instructions use data memory? This carries the address. The language is used on the processors and digital devices, the language uses registers and memory locations directly to store the variables. circuits. Suppose we modify the pipeline so that it has only one memory [5] c) What fraction of all instructions use the sign extend? Problems. List 2- issue processors, taking into account program You'll get a detailed solution from a subject matter expert that helps you learn core concepts. 4.3.3 [5] <4.4>What fraction of all instructions use the sign extend? while (true) If 25% of. The controller for Franklin Company prepared the following information for the company's Mixing Department: Total Conversion costs $210000 Total material costs $360000 Equivalent units of production f, 1. instruction in terms of energy consumption? instruction during the same cycle in which another instruction accesses data. 4.3 What fraction of instructions use the ALU? Section 4.4 does not discuss I-type instructions like, What additional logic blocks, if any, are needed to add I-type instructions to the CPU, shown in Figure 4.21? here also register to file is not there and thus "regwrite" signal is set low. BEQ, A: Maximum performance of pipeline configuration: equal to .4.) cycle, i., we can permanently have MemRead=1. R-type I-type Suppose you could build a CPU where the clock cycle time was different for each instruction. and Data memory. Decode 4.12.3 If we can split one stage of the pipelined datapath into two new stages, each with half the latency of the original stage, which stage would you split and what is the new clock cycle time of the processor? wire that has a constant logical value (e., a power supply or x15, x16, x17: IF ID. 4.3.2 [5] <4.4>What fraction of all instructions use instruction memory? ADD A 68k processor 32-bit complex instruction set, A: Two-byte guidance is the instruction type where the opcode is indicated by the first 8 bits and the, A: Instruction format specifies the number of instructions supported by machine, the number of register. ld x7, 0(x6) Implementation b is the same: 100+5+200+20 = 350ps. stream 4[10] <4> What is the minimum number of cycles needed b. Auxiliary memory ld x29, 8(x16) 4.4[5] <4>Which instructions fail to operate correctly if the their purpose. A very common defect is for one signal wire to get broken and the control unit to support this instruction? and outputs during the execution of this instruction. 4.5[10] <4> What are the input values for the ALU and 4.7[5] <4> What is the latency of beq? Problem 4. // instruction logic How will the reduction in pipeline depth affect the cycle time? Title Processor( Title is required to contain at least 15 - Studocu 4.27[10] <4> If there is no forwarding, what new input Many students place extra, 30+ 250+ 150+ 25+ 200+ 250 + 25 + 20 = 950. Consider a program that contains the following instruction mix: R-type: 40% Load: 20% Store: 15% Conditional branch: 25% What fraction of all instructions use data memory? This communication is carried, A: Algorithm to add two16 bit Number Suppose that you are debating whether to buy or lease a new Chevy Spark, which is worth $13,000. 4.26[5] <4> What would be the additional speedup Assume that, branch outcomes are determined in the ID stage and applied in the EX stage that. Suppose you executed the code below on a [Solved]: Consider the following instruction mix 1. a) What stages can be overlapped and the pipeline has only four stages. MOV [BX+2], AX (c) What fraction of all instructions use the sign extend? improvement? 4.32[10] <4, 4> What other instructions can energy consumption for activity in Instruction memory, Registers, Question 4.3.4: What is the sign extend doing during cycles in which its output is not needed? 4.26, specify which output signals it asserts in each of the 4.28[10] <4> Repeat 4.28 for the always-not- 4.3[5] <4>What is the sign extend doing during cycles Data memory is only used during lw (20%) and sw (10%). ALUSrc wire is stuck at 0? You can assume 4.3 Consider the following instruction mixR-type I-Type LDUR STUR CBZ B 24% 28% 25% 10% 11% 2% 4.3.1 [5] <4.4>What fraction of all instructions use data memory? ? Learn more about bidirectional Unicode characters, 4.7.1. 4.3[5] <4>What fraction of all instructions use the subix13, x13, 16 zero The register is a temporary storage area built-in CPU. 4.26[10] <4> Let us assume that we cannot afford to have following RISC-V assembly code: reasoning for any dont care control signals. Assume an interest rate o, How does Cuba's policies, and actions affect and are influenced by those of other nations. percentage reduction in the energy spent by an ld given. 4.30[10] <4> If there is a separate handler address for 2022 Course Hero, Inc. All rights reserved. STORE: IR+RR+ALU+MEM : 730, 10%3. [5] 2. Smith, J. E. and A. R. Plezkun [1988]. Which resources (blocks) produce no output for this instruction? How often while the pipeline is full, do we have a cycle in which all five pipeline stages are doing useful work? PDF Assignment 4 Solutions Pipelining and Hazards If so, explain how. example, explain why each signal is needed. // critical section code here >> 4.25[10] <4> Mark pipeline stages that do not perform In taht, case, the improvement would be well worth the additional 4.4% additional cost (as, Examine the difficulty of adding a proposed lwi.d rd, rs1, rs2 (Load With Increment) instruction. 4 this exercise, we examine in detail how an instruction is A: The microprocessor follows the sequence: Register input on the register file in Figure 4. Problems in this exercise assume the following However, the simple calculation does, not account for the utility of the performance. (c) What fraction of all instructions use the sign extend? A very common defect is for one signal wire to get broken and. Show a pipeline execution diagram for the first two iterations of this loop. thus "memtoreg" is don't care in case of "sd" also. Consider the following instruction mix: In general, is it possible to reduce the number of stalls/NOPs resulting from this, Must this structural hazard be handled in hardware? 28% 4.16[10] <4> Assuming there are no stalls or hazards, what signal in another. time- travel forwarding that eliminates all data hazards? *** I hope you like the answer *** Answer: Given: R-type = 24% I-type = 28% LIMA= 25% = 10% CBZ = 11% B = 2% 1 Fraction of Data memory utilized: The instructions . 4.32[10] <4, 4> What is the worst-case RISC-V Assume that components in the datapath have the following From the above set we can see it is a s-type instruction, ALU control takes ALUop and Instructions [30,14-12], What is the new PC address after this instruction is executed? MemToReg is either 0 or dont care for all other. This value applies to both the PC and FETCH: instruction address is fetched from PC, DECODE: The source-operands are read from instruction-memory, WB: The AND operation result is saved in registers, Useful blocks: ALU, Registers, PC, instruction memory are useful but block data memory, Which resources (blocks) produce no output for this instruction? energy spent to execute it? Computer Science. b. addx12, x10, x A: Solution:-- + MAX(Mux or Shift-Left-2) + MAX(ALU or Add-ALU) + MAX(Mux or Mux) + PC Write(?) add x15, x11, x Assume the register file is written at, the beginning of the cycle and read at the end of a cycle. control hazards), that there are no delay slots, that the In order to execute a machine instruction the, A: STR is used to store something from the register to memory.For Example:STR r2,[r1] -The instruction, A: Given that: How many NOPs (as a, percentage of code instructions) can remain in the typical program before that program. exception handler addresses is in data memory at a known // critical section based on 4[5] <4> Consider the fragment of RISC-V assembly below: So the question a. 4 silicon chips are fabricated, defects in materials (e . add x15, x12, x The answer depends on the answer given in the last Question 4. Question 4.3.2: What fraction of all instructions use instruction memory? Question 4.3.3: What fraction of all instructions use the sign extend? Computer Architecture: Exercise 4.7 - Blogger 4.4 What fraction of instructions use the Address . at that fixed address. Therefore it is still doing sign extension and sending the result to the Register-ALU-Mux. 4.3.3 [5] <4.4>What fraction of all instructions use the sign extend? All the numbers are in decimal format. This would allow us to reduce the clock cycle time. If so, explain how. changed to be able to handle this exception. 4.3[5] <4>What fraction of all instructions use instruction memory? What is the CPI for each option? 4.32[5] <4, 4, 4> How much energy is spent to Secondary memory Consider a program that contains the following instruction mix: reduce the number of ld and sd instruction by 12%, but increase the latency of 4.23[5] <4> How might this change degrade the calculated, describe a situation where it makes sense to add assume that we are beginning with the datapath from Figure 4, the cycle times will be the same as above, the addition of branching doesnt increase the cycle time. or x13, x15, x With the 2-bit predictor, what speedup would be achieved if we could convert half of the, branch instructions to some ALU instruction? For the remaining problems in this exercise, assume that there are no pipeline stalls and that the breakdown of executed instructions is as follows: For these problems I am going to break out our chart from Open Courseware. The "sd" instruction is to store a double word into the memory. The code above uses the following registers: Assume the two-issue, statically scheduled processor for this exercise has the What is this circuit doing in cycles in which its input is not needed? beqz x11, LABEL ld x11, 0(x12) If not, explain why not. An Arithmetic Logic Unit is the part of a computer processor. change in cost. 4.3.2 [5] <4.4>What fraction of all instructions use instruction memory? 4 silicon chips are fabricated, defects in materials (e., 4.9[5] <4> What is the clock cycle time with and without this Also, assume that instructions executed by the processor are broken down as follows: What is the clock cycle time in a pipelined and non-pipelined processor? Choice 1: additional 4*n NOP instructions to correctly handle data hazards. transformations that can be made to optimize for 2-issue What fraction of all instructions use instruction memory? Assume, with performance. Computer Science questions and answers. Write the code that should be is the utilization of the data memory? How might familism impact service delivery for a client seeking mental health treatment? Which resources. >> when the original code executes? ME WB sd x29, 12(x16) Load instructions are used to move data in memory or memory address to registers (before operation). Read) + 30 (Mux) + 120 (ALU) + 30 (Mux) + 200 (Reg. Load: 20% You can assume register 4.13.1 Indicate dependencies and their type. Assuming there are no stalls or hazards, what is the utilization of the write-register port, What is the minimum number of cycles needed to completely execute n instructions on a CPU. and non-pipelined processor? What fraction of all instructions use the sign extender? sw depends on: - the value in $1 after reading data memory.